From RHLUG

Xilinx ISE is used to generate bitstreams for programming their FPGAs.

[edit] Installing

The files needed to install Xilinx are on tibia, in the same place as the Windows files (\\tibia\Public\Course Software\Xilinx). That installer, however, requires libstdc++5. Copy the files to your computer (grab the entire folder "Install-Me-First_WebPACK_92i"), and run the file <InstallMeFirst>/bin/lin/setup. It will ask you where you want to install Xilinx. Under a regular user, it will not try to put files in the "right" place. When the installer finishes, it will tell you to source a particular .sh file (settings.sh or settings.csh). If using the default install location (for regular users) of ~/Xilinx92i, then bash users can add "source ~/Xilinx92i/settings.sh" to their ~/.bashrc. After the source command runs, Xilinx should be setup and ready to go.

[edit] Programming

The Nexys 2 can be programmed by following the instructions at this page. Make sure your Xilinx directory is named "ISE" (this is not the default!), and that the script is located in the same directory as "ISE". From their, it should work after one or two runs.

The original Nexys can be programmed in a similar way, however the exact script may not be compatible. The Spartan 3 used in ECE130 may not be compatible with the method outlined at the above link.

[edit] mkfile for synthesis

Rather than using the included GUI, I prefer to use a mkfile:

# mkfile for synthesis of verilog with Xilinx ISE
# Michael Auchter
# to generate bitstream, type: mk $PNAME.bit


MKSHELL = rc 
# part-package-speed, xc3s400-ft256-4 for digilent nexys 2
FPGA = xc3s400-ft256-4
# name of your project.  this is arbitrary.
PNAME = project1
UCF = nexys.ucf
VFILES = `{ls *.v | grep -v _tb\.v}


default: $PNAME.ngc

$PNAME.ver:: $VFILES
        echo $prereq | sed 's/[ ]\+/\n/g' | sed 's/.*/`include "&"/g;' > $target 

$PNAME.scr:: $PNAME.ver
        echo run -ifn $prereq -ifmt Verilog -ofn $PNAME^.ngc -ofmt NGC > $target
        echo -p $FPGA -opt_mode Speed -opt_level 1 >> $target

$PNAME.ngc:: $PNAME.ver $PNAME.scr
        xst -ifn $PNAME.scr

$PNAME.ngd:: $PNAME.ngc $UCF
        ngdbuild -p $FPGA -uc $UCF $PNAME.ngc

$PNAME.map.ncd:: $PNAME.ngd
        map -p $FPGA -o $target $prereq

$PNAME.ncd:: $PNAME.map.ncd
        par $prereq -w $target

$PNAME.bit:: $PNAME.ncd
        bitgen $prereq -w $target